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AT91SAM9261-EK Evaluation Board
..............................................................................................
User Guide
AT91SAM9261-EK Evaluation Board User Guide
6198A-ATARM-15-Nov-05
Table of Contents
Section 1 Overview............................................................................................... 1-1
1.1 1.2 1.3 Scope........................................................................................................1-1 Deliverables ..............................................................................................1-1 The AT91SAM9261-EK Evaluation Board ................................................1-1
Section 2 Setting Up the AT91SAM9261-EK Evaluation Board ........................... 2-1
2.1 2.2 2.3 2.4 2.5 2.6 2.7 Electrostatic Warning ................................................................................2-1 Requirements............................................................................................2-1 Layout .......................................................................................................2-2 Powering Up the Board .............................................................................2-3 Backup Power Supply ...............................................................................2-4 Getting Started..........................................................................................2-4 AT91SAM9261-EK Block Diagram ...........................................................2-4
Section 3 Board Description ................................................................................. 3-1
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 AT91SAM9261 Microcontroller .................................................................3-1 AT91SAM9261 Block Diagram .................................................................3-4 Memory .....................................................................................................3-5 Clock Circuitry ...........................................................................................3-5 Reset Circuitry ..........................................................................................3-5 Shutdown Controller .................................................................................3-5 Power Supply Circuitry..............................................................................3-5 Remote Communication ...........................................................................3-5 Audio Stereo Interface ..............................................................................3-5 User Interface ...........................................................................................3-5 Debug Interface ........................................................................................3-6 Expansion Slot ..........................................................................................3-6
Section 4 Configuration Straps ............................................................................. 4-1
4.1 Configuration Straps .................................................................................4-1
Section 5 Schematics ........................................................................................... 5-1
5.1 Schematics ...............................................................................................5-1
AT91SAM9261-EK Evaluation Board User Guide
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AT91SAM9261-EK Evaluation Board User Guide
Section 1 Overview
1.1
Scope
The AT91SAM9261-EK evaluation kit is an effective platform for evaluating chip performance and developing code for applications based on the AT91SAM9261. This guide is a description of the hardware included in the AT91SAM9261-EK evaluation kit. Software files are available on the DVD-ROM included in the kit and described in "Deliverables" below.
1.2
Deliverables
The AT91SAM9261-EK package contains the following items: ! an AT91SAM9261-EK board ! one A/B-type USB cable ! one serial RS232 cable ! one RJ45 crossed Ethernet cable ! one DataFlash(R) card ! universal input AC/DC power supply with US and EU plug adapter ! one DVD-ROM containing summary and full datasheets, datasheets with electrical and mechanical characteristics, application notes and getting started documents for all development boards and AT91 microcontrollers. An AT91 software package with C and assembly listings is also provided. This allows the user to begin evaluating the AT91 ARM(R) Thumb(R) 32-bit microcontroller quickly.
1.3
The AT91SAM9261EK Evaluation Board
The board is equipped with an AT91SAM9261 (217-ball LFBGA package) together with the following: ! 64 Mbytes of SDRAM memory ! 256 Mbytes of NAND Flash memory ! one Atmel 32 Mbit serial DataFlash (AT45DB321C-CNC) ! one USB device port interface ! two USB host port interfaces ! one DBGU serial communication port
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Overview
! JTAG/ICE debug interface ! one Ethernet 100-base TX with three status LEDs ! one Atmel AT73C213 Audio DAC ! one 3.5" 1/4 VGA TFT LCD Module with TouchScreen and backlight ! one Power LED and two general-purpose LEDs ! four user input pushbuttons ! one wakeup input pushbutton ! one reset pushbutton ! one DataFlash SD/MMC card slot ! two expansion footprint connectors (solder side) ! one Lithium Coin Cell Battery Retainer for 12 mm cell size ! dual pitch prototyping area
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AT91SAM9261-EK Evaluation Board User Guide
Section 2 Setting Up the AT91SAM9261-EK Evaluation Board
2.1
Electrostatic Warning
The AT91SAM9261-EK evaluation board is shipped in a protective anti-static package. The board must not be subjected to high electrostatic potentials. A grounding strap or similar protective device should be worn when handling the board. Avoid touching the component pins or any other metallic element.
2.2
Requirements
In order to set up the AT91SAM9261-EK evaluation board, the following items are required: ! the AT91SAM9261-EK evaluation board itself ! AC/DC power adapter (5V at 2A), 2.1 mm by 5.5 mm
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Setting Up the AT91SAM9261-EK Evaluation Board
2.3
Layout
Figure 2-1. AT91SAM9261-EK Layout - Top View
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AT91SAM9261-EK Evaluation Board User Guide
Setting Up the AT91SAM9261-EK Evaluation Board
Figure 2-2. AT91SAM9261-EK Layout - Bottom View
2.4
Powering Up the Board
AT91SAM9261-EK requires 5V DC (5%). DC power is supplied to the board via the 2.1 mm by 5.5 mm socket (J1). The coaxial power plug center pin is positive polarity .
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Setting Up the AT91SAM9261-EK Evaluation Board
2.5
Backup Power Supply
The user has the possibility to add a battery (3V Lithium Battery CR1225 or equivalent) in order to permanently power the backup part of the device. In this case, J9 configuration must to be set in position 1, 2. Refer to Table 4-1, "Configuration Jumpers and Straps".
2.6
Getting Started
The AT91SAM9261-EK evaluation board is delivered with a DVD-ROM containing all necessary information and step-by-step procedures for working with the most common development tool chains. Please refer to this DVD-ROM, or to the AT91 web site, http://www.atmel.com/products/AT91/, for the most up-to-date information on getting started with the AT91SAM9261-EK.
2.7
AT91SAM9261EK Block Diagram
Figure 2-3. Block Diagram
ETHERNET 10/100 JTAG/ICE RJ45
DBGU RS232
HEADPHONE OUT
TFT 320 x 240 1/4 VGA DISPLAY WITH TOUCHSCREEN
A
ADM3202A POWER SUPPLY 5 VDC LINEAR REGULATOR VDD3V3 3V3 YELLOW POWER LED 5V SHUTDOWN TRACE PORT ETM EMAC + PHY AT73C213 STEREO AUDIO DAC
B
VUSB
RXD
TXD
DRXD - DTXD
HDMA - HDPA
HDMB - HDPB
CONTROLLER SCC1 I2S
NRST
PA11..PA31
USB HOST
VDDCORE
USB DEVICE
1V2
NRST
DBGU
REG 1V2
PA29 / SPI0_NPCS3
SPI0_NPCS2
1V2
SCC1
EBI
SHUTDOWN
VDDPLL VDDOSC
VDDIO XOUT
SYSTEM CONTROLLER
AT91SAM9261-BGA217
SPI0_NPCS3 / PA6 SPI0_NPCS0 EBI SPI0 MCI
XIN GNDBU VDDBU PIO WKUP SHDN
EXT CLK INPUT
SPI0
LCD CONTROLLER
1V2
3V +
3 2 1
1.2V 16 SDRAM 256 Mb 3V3 USER'S GREEN LED
3 2 1
32 16 SDRAM 256 Mb 16 NANDFLASH 512 Mb
32 Mbits DATAFLASH AT45D321C-CNC
912345678
SD/MMC DATAFLASH CARD READER
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CS
MISO - MOSI - SPCK
EXPANSION CONNECTORS
PIO
TOUCHSCREEN
DDM
DDP
LCD CONTROL
18.432 MHz
Section 3 Board Description
3.1
AT91SAM9261 Microcontroller
! Incorporates the ARM926EJ-STM ARM(R) Thumb(R) Processor - DSP Instruction Extensions - ARM Jazelle(R) Technology for JavaTM Acceleration - 16-KByte Data Cache, 16-KByte Instruction Cache, Write Buffer - 200 MIPS at 180 MHz - Memory Management Unit - EmbeddedICETM In-circuit Emulation, Debug Communication Channel Support - Mid-level implementation Embedded Trace MacrocellTM ! Additional Embedded Memories - 32K Bytes of Internal ROM, Single-cycle Access at Maximum Bus Speed - 160K Bytes of Internal SRAM, Single-cycle Access at Maximum Processor or Bus Speed ! External Bus Interface (EBI) - Supports SDRAM, Static Memory, NAND Flash and CompactFlash(R) ! LCD Controller - Supports Passive or Active Displays - Up to 16-bits per Pixel in STN Color Mode - Up to 16M Colors in TFT Mode (24-bit per Pixel), Resolution up to 2048 x 2048 ! USB - USB 2.0 Full Speed (12 Mbits per second) Host Double Port Dual On-chip Transceivers Integrated FIFOs and Dedicated DMA Channels - USB 2.0 Full Speed (12 Mbits per second) Device Port On-chip Transceiver, 2-Kbyte Configurable Integrated FIFOs ! Bus Matrix - Handles Five Masters and Five Slaves - Boot Mode Select Option
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Board Description
- Remap Command ! Fully Featured System Controller (SYSC) for Efficient System Management, including - Reset Controller, Shutdown Controller, Four 32-bit Battery Backup Registers for a Total of 16 Bytes - Clock Generator and Power Management Controller - Advanced Interrupt Controller and Debug Unit - Periodic Interval Timer, Watchdog Timer and Real-time Timer - Three 32-bit PIO Controllers ! Reset Controller (RSTC) - Based on Power-on Reset Cells, Reset Source Identification and Reset Output Control ! Shutdown Controller (SHDWC) - Programmable Shutdown Pin Control and Wake-up Circuitry ! Clock Generator (CKGR) - 32.768 kHz Low-power Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock - 3 to 20 MHz On-chip Oscillator and two PLLs ! Power Management Controller (PMC) - Very Slow Clock Operating Optimization Capabilities ! Advanced Interrupt Controller (AIC) - Individually Maskable, Eight-level Priority, Vectored Interrupt Sources - Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected ! Debug Unit (DBGU) - 2-wire USART and Support for Programmable ICE Access Prevention ! Periodic Interval Timer (PIT) - 20-bit Interval Timer plus 12-bit Interval Counter ! Watchdog Timer (WDT) - Key Protected, Programmable Only Once, Windowed 12-bit Counter, Running at Slow Clock ! Real-Time Timer (RTT) - 32-bit Free-running Backup Counter Running at Slow Clock ! Three 32-bit Parallel Input/Output Controllers (PIO) PIOA, PIOB and PIOC - 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os - Input Change Interrupt Capability on Each I/O Line - Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output ! Nineteen Peripheral DMA (PDC) Channels Debug Communication Channel, Mode, Software Programmable Power
- Four Programmable External Clock Signals
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Board Description
! Multimedia Card Interface (MCI) - Compliant with Multimedia Cards and SDCards - Automatic Protocol Control and Fast Automatic Data Transfers with PDC, MMC and SDCard Compliant ! Three Synchronous Serial Controllers (SSC) - Independent Clock and Frame Sync Signals for Each Receiver and Transmitter - IS Analog Interface Support, Time Division Multiplex Support - High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer ! Three Universal Synchronous/Asynchronous Receiver Transmitters (USART) - Individual Baud Rate Generator, IrDA Infrared Modulation/Demodulation - Support for ISO7816 T0/T1 Handshaking, RS485 Support Smart Card, Hardware and Software
! Two Master/Slave Serial Peripheral Interface (SPI) - 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects ! One Three-channel 16-bit Timer/Counters (TC) - Three External Clock Inputs, Two multi-purpose I/O Pins per Channel - Double PWM Generation, Capture/Waveform Mode, Up/Down Capability ! Two-wire Interface (TWI) - Master Mode Support, All Two-wire Atmel EEPROMs Supported ! IEEE 1149.1 JTAG Boundary Scan on All Digital Pins ! Required Power Supplies: - 1.08V to 1.32V for VDDCORE and VDDBU - 2.7V to 3.6V for VDDOSC and for VDDPLL - 2.7V to 3.6V for VDDIOP (Peripheral I/Os) and for VDDIOM (Memory I/Os) ! Available in a 217-ball LFBGA RoHS-compliant Package
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Board Description
3.2
AT91SAM9261 Block Diagram
JTAGSEL TDI TDO TMS TCK NTRST RTCK
Figure 3-1. Block Diagram
ARM926EJ-S Core
ICE Instruction Cache 16K bytes TCM Interface
I D I D
MMU
Data Cache 16K bytes BIU
ETM
PIO
JTAG Boundary Scan
TSYNC TCLK TPS0-TPS2 TPK0-TPK15 BMS D0-D15 A0/NBS0 A1/NBS2/NWR2 A2-A15/A18-A21 A22/REG A16/BA0 A17/BA1 NCS0 NCS1/SDCS NCS2 NCS3/NANDCS NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW SDCK SDCKE RAS-CAS SDWE SDA10 NWAIT A23-A24 A25/CFRNW NCS4/CFCS0 NCS5/CFCS1 CFCE1 CFCE2 NCS6/NANDOE NCS7/NANDWE D16-D31 HDMA HDPA HDMB HDPB
System Controller TST FIQ IRQ0-IRQ2 DRXD DTXD PCK0-PCK3 PLLRCA PLLRCB XIN XOUT AIC PIO DBGU PDC
ITCM
DTCM
EBI CompactFlash NAND Flash
Fast SRAM 160K bytes
PLLA PLLB OSC PMC Fast ROM 32K bytes 5-layer Matrix PIT Peripheral Bridge Peripheral DMA Controller DMA RSTC POR APB PIOA PIOB PIOC FIFO USB Device USB Host FIFO Transceiver Transceiver
WDT
SDRAM Controller
GPBREG XIN32 XOUT32 SHDN WKUP VDDBU GNDBU VDDCORE NRST POR OSC RTT SHDWC
Static Memory Controller
PIO
DDM DDP
DMA MCCK MCCDA MCDA0-MCDA3 FIFO MCI PDC RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 RTS1 CTS1 RXD2 TXD2 SCK2 RTS2 CTS2 SPI0_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 SPI0_MISO SPI0_MOSI SPI0_SPCK SPI1_NPCS10 SPI1_NPCS1 SPI1_NPCS12 SPI1_NPCS3 SPI1_MISO SPI1_MOSI SPI1_SPCK LUT LCD Controller LCDD0-LCDD23 LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDCC TF0 TK0 TD0 RD0 RK0 RF0 TF1 TK1 TD1 RD1 RK1 RF1 TF2 TK2 TD2 RD2 RK2 RF2 TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 TWD TWCK
USART0 PDC PDC
SSC0
USART1
PIO PIO
SSC1 PDC PDC PIO SSC2 PDC Timer Counter TC0 TC1 TC2 TWI PDC
USART2 PDC
SPI0 PDC
SPI1
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Board Description
3.3
Memory
! 32 Kbytes of Internal ROM ! 160 Kbytes of Internal High-speed SRAM ! Atmel 32 Mbit serial DataFlash ! 64 Mbytes of SDRAM memory ! 256 Mbytes of NAND Flash memory
3.4
Clock Circuitry
! 18.432 MHz standard crystal for the embedded oscillator ! 32.768 kHz standard crystal for the slow clock oscillator
3.5
Reset Circuitry
! Internal reset controller with a bi-directional reset pin ! External reset push button
3.6
Shutdown Controller
! Programmable shutdown and Wake-Up ! Wake-up push button
3.7
Power Supply Circuitry
! For dynamic power consumption, the AT91SAM9261 consumes a maximum of 50 mA on VDDCORE at maximum speed in typical conditions (1.2V, 25C), processor running full-performance algorithm ! On-board 1.2V high efficiency step-down charge pump regulator with shutdown control ! On-board 3.3V linear regulator with shutdown control
3.8
Remote Communication
! One Serial interface (DBGU COM Port) via RS-232 DB9 male socket ! USB V2.0 Full-speed Compliant, 12 Mbits per second (UDP) ! Two USB Host port V2.0 Full-speed Compliant, 12 Mbits per second (UHP) ! One Ethernet 100-base TX with three status LEDs
3.9
Audio Stereo Interface
! One Atmel stereo audio DAC AT73C213 ! One 32 Ohm/20 mW Stereo Headset output (J20) with Master Volume and Mute Controls
3.10
User Interface
! Four user input pushbuttons ! Two user green LEDs ! One yellow power LED (can be also software controlled)
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Board Description
! One 1/4 VGA display LCD with Touchscreen and white LED backlight
3.11
Debug Interface
! 20-pin JTAG/ICE interface connector ! DBGU COM Port
3.12
Expansion Slot
! One DataFlash, SD/MMC card slot ! All I/Os of the AT91SAM9261 are routed to peripheral extension footprint connectors (J16 and J17). This allows the developer to check the integrity of the components and to extend the features of the board by adding external hardware components or boards.
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Section 4 Configuration Straps
4.1
Configuration Straps
Table 4-1 gives details on configuration straps on the AT91SAM9261-EK evaluation board and their default settings. Table 4-1. Configuration Jumpers and Straps
Designation J2 Default Setting Closed Feature 3.3V Jumper (1) This jumper footprint is provided for 3.3V power consumption measurement use. By default, it is closed. To use this feature, the user has to open the strap by cutting it before soldering a jumper. Forces power on. To use the software shutdown control, J3 must be opened. Enables Boot on the internal ROM Enables Boot on the NCS0 VDDPLL Jumper (1) VDDBU Jumper select (1) 1-2 : Lithium 3V Battery 2-3 : 1.2V from VDDCORE VDDCORE Jumper (1) NPCS0 select 1-2 : AT45DB321C (MN7) 2-3 : Dataflash card interface (J22). Warning: In this case NPCS03 must be configured as input. Disables the ICE NTRST input Enables the ICE RTCK return. S6 must be opened Enables the ICE NRST input Selects ICE mode or JTAG mode (Closed) Disables TCK <-> RTCK local loop. If S6 is closed, S3 must be opened.
J3 J4
Closed Opened Closed
J8 J9
Closed 2-3
J12 J21
Closed 1-2
S2 S3 S4 S5 S6
Opened Closed Closed Opened Opened
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Configuration Straps
Table 4-1. Configuration Jumpers and Straps
Designation S7-S8 S9 S10 S12 S13 S14 S15 S16 S19 S20 S21 S22 S23 S24 S25 S26 TP1 TP2 TP3 TP4 TP63 TP64 TP65 TP66 Note: Default Setting Closed Opened Closed Opened Closed Closed Closed Opened Closed Closed Closed Closed Closed Closed Closed Closed N.A N.A N.A N.A N.A N.A N.A N.A Feature Enables the use of 18.432 MHz crystal. If external clock used, S7-S8 must be opened and S9 closed. Enables the use of SDRAM (NCS1_SDCS) Disables Serial DataFlash write protect. Disables NAND FLASH write protect. Enables the use of interrupt ETHERNET MAC (PC11_FIQ). Enables the use of ETHERNET MAC (NCS2). Disables the use of NWAIT ETHERNET MAC signal (PC2_NWAIT) Enables the use of the User LED DS7 (PA14) Enables the use of the User LED DS8 (PA13) Enables the use of the DBGU RXD signal (PA9) Enables the use of the USB CNX detection (PB29) Enables the use of AUDIO DAC INTERFACE (NPCS03) Enables the use of TOUCH SCEEN CONTROLLER (NPCS02) Enables the use of TOUCH SCEEN CONTROLLER BUSY signal (PA11) Enables the use of TOUCH SCEEN CONTROLLER PENIRQ (PC2_IRQ0) 3.3V Test point. GND Test point. 1.2V Test point. GND Test point. 0 to 3.3V analog user's input 0 to 3.3V analog user's input AGND of TP63 AGND of TP64
1. These jumpers are provided for measuring power consumption. By default, they are closed. To use this feature, the user has to open the strap and insert an anmeter.
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Section 5 Schematics
5.1
Schematics
This section contains the following schematics: ! Power Supply and Audio ! AT91SAM9261 ! SDRAM and NAND Flash ! Ethernet ! LCD and User Interface ! Serial and I/O Expansion
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3V3 10 SQUARE CM COPPER AREA FOR HEAT SINKING WITH NO SOLDER MASK LT1963AEQ-3.3 6 MN1 R1 120R 3V3 J2
AUDIO DAC INTERFACE
3V3
REGULATED 5V ONLY J1
5V
R2 100K
1 2
+ C1 330F
C2 10F 10V 2
GND VIN SD VOUT GND 3 FB 5 4
POWER LED
TP1 3.3V R67 100K DS1 YELLOW PA[0..31] MN15 AT73C213
DOUT DIN CLK CS SMODE RSTB
PA[0..31] PA0 PA1 PA2 PA29
CR1 5V
1
C3 10F
C4 10F TP2 GND
3
Q1 IRLML2402
15 12 14 13 11 10 16
PAINN VBAT CBP HPP HPN LPHN PAINP MONOP MONON
25 26 27 28 22 21 24 2 5 9 1
SPI0_MISO SPI0_MOSI SPI0_SPCK SPI0_NPCS3 S23 NRST
3
1
M5V C5 1F
C
PA23
2
C6 1F
30 29 7
VDIG
3V3 VCC_DAC
C
AVDD LINER AVDDHS LINEL VCM AUXP VREF AUXN
Q2 6 Si1563EDH
5
4
5V
8 C1M 5 VIN
6
3
4 C2P VOUT 7
1V2 C7 R3 22F 100K C8 10PF TP3 1.2V J20 3.5 PHONEJACK STEREO 3 1 4 2 TP4 GND C112 + 100F 6V3
C1P C2M
6 31 32 4 3
C113 + 100F 6V3
C107 10F C111 10F
J3 FORCE POWER ON C9 15PF
C110 100NF C108 C109 100NF 100NF GND_DAC PB31 PCK2 PA19 TD1 PA17 TF1 PA18 TK1
1
2
R5 10K
3
R6 10K
TPS60500 C10 4.7F
PB[0..31]
FB 1 EN
MN2
10 2
R4 200K
HSR
GND 9
PG
HSL
MCLK SDIN LRFS BCLK
20 17 19 18
R68 47R
SHDN
INGND
GNDB
GNDD
PA[0..31]
8
33
23
ADHESIVE FEET Z3 11.1
B
GND_DAC VCC_DAC L4 4.7H 3V3
B
Z4 11.1
Z7 11.1
Z8 11.1
C114 10F 10V R69 0R GND_DAC
A
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Wednesday, September 14, 2005
C B A INIT EDIT
REV MODIF.
JPG JPG JPG
DES.
14/09/05 04/20/05 02/23/05
DATE
XXX
VER. REV.
XX/XX/05
DATE SHEET
AT91SAM9261-EK
POWER SUPPLY & AUDIO
SCALE
1/1
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This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
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PC[0..15] PB[0..31] PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 BOOT MODE SELECT PB3 R7 1K J4 PA[0..31] MN3 BMS D[0..31] A[0..22]
L17 K16 K17 K15 J17 H17 J16 H16 G17 J15 H14 G16 G15 H15 G14 E16 F14 D16 E15 B17 D15 C16 E14 D14 A17 B16 B15 A15 D13 D12 C13 B13 LCDVSYNC/PB0 LCDHSYNK/PB1 LCDDOTCK/PCK0/PB2 BMS/LCDDEN/PB3 LCDCC/LCDD2/PB4 LCDD0/LCDD3/PB5 LCDD1/LCDD4/PB6 LCDD2/LCDD5/PB7 LCDD3/LCDD6/PB8 LCDD4/LCDD7/PB9 LCDD5/LCDD10/PB10 LCDD6/LCDD11/PB11 LCDD7/LCDD12/PB12 LCDD8/LCDD13/PB13 LCDD9/LCDD14/PB14 LCDD10/LCDD15/PB15 LCDD11/LCDD19/PB16 LCDD12/LCDD20/PB17 LCDD13/LCDD21/PB18 LCDD14/LCDD22/PB19 LCDD15/LCDD23/PB20 TF0/LCDD16/PB21 TK0/LCDD17/PB22 TD0/LCDD18/PB23 RD0/LCDD19/PB24 RK0/LCDD20/PB25 RF0/LCDD21/PB26 SPI1_NPCS1/LCDD22/PB27 SPI1_NPCS0/LCDD23/PB28 SPI1_SPCK/IRQ2/PB29 SPI1_MISO/IRQ1/PB30 SPI1_MOSI/PCK2/PB31
D
ETM TRACE PORT
PA13 PA14 PA15 PA11 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 3V3 R8 10K PA12 PIPESTAT[0] PIPESTAT[1] PIPESTAT[2] TRACESYNC TRACEPKT[0] TRACEPKT[1] TRACEPKT[2] TRACEPKT[3] TRACEPKT[4] TRACEPKT[5] TRACEPKT[6] TRACEPKT[7] VSUPPLY EXTTRIG TRACECLK R9 0R C11 100NF
38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
TRACEPKT[8] TRACEPKT[9] TRACEPKT[10] TRACEPKT[11] TRACEPKT[12] TRACEPKT[13] TRACEPKT[14] TRACEPKT[15] ICE_NTRST TDI TMS TCK ICE_RTCK TDO ICE_NRST DBGRQ GND
PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31
R10 10K
J5
C
DNP
3V3
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31
R11 T12 U13 P10 T13 U14 T14 R12 T15 U16 R13 T16 U15 R14 T17 P13 P14 R15 R17 P16 P17 N15 N14 N16 N17 M14 M15 L15 M16 M17 L14 L16 A12 B12 C12 B14 A13 A14 E17 C17 D17 U17 F16 B10 F17
PA0/SPI0_MISO/MCDA0 PA1/SPI0_MOSI/MCCDA PA2/SPI0_SPCK/MCCK PA3/SPI0_NPCS0 PA4/SPI0_NPCS1/MCDA1 PA5/SPI0_NPCS2/MCDA2 PA6/SPI0_NPCS3/MCDA3 PA7/TWD/PCK0 PA8/TWCK/PCK1 PA9/DRXD/PCK2 PA10/DTXD/PCK3 PA11/TSYNK/SCK1 PA12/TCLK/RTS1 PA13/TPS0/CTS1 PA14/TPS1/SCK2 PA15/TPS2/RTS2 PA16/TPK0/CTS2 PA17/TPK1/TF1 PA18/TPK2/TK1 PA19/TPK3/TD1 PA20/TPK4/RD1 PA21/TPK5/RK1 PA22/TPK6/RF1 PA23/TPK7/RTS0 PA24/TPK8/SPI1_NPCS1 PA25/TPK9/SPI1_NPCS2 PA26/TPK10/SPI1_NPCS3 PA27/TPK11/SPI0_NPCS1 PA28/TPK12/SPI0_NPCS2 PA29/TPK13/SPI0_NPCS3 PA30/TPK14/A23 PA31/TPK15/A24 DDP DDM HDPA HDMA HDPB HDMB TDI TMS TCK RTCK TDO JTAGSEL NTRST PLLRCB
NANDOE/NCS6/PC0 NANDWE/NCS7/PC1 NWAIT/IRQ0/PC2 A25/CFRNW/PC3 NCS4/CFCS0/PC4 NCS5/CFCS1/PC5 CFCE1/PC6 CFCE2/PC7 TXD0/PCK2/PC8 RXD0/PCK3/PC9 RTS0/SCK0/PC10 CTS0/FIQ/PC11 TXD1/NCS6/PC12 RXD1/NCS7/PC13 TXD2/SPI1_NPCS2/PC14 RXD2/SPI1_NPCS3/PC15 D16/TCLK0/PC16 D17/TCLK1/PC17 D18/TCLK2/PC18 D19/TIOA0/PC19 D20/TIOB0/PC20 D21/TIOA1/PC21 D22/TIOB1/PC22 D23/TIOA2/PC23 D24/TIOB2/PC24 D25/TF2/PC25 D26/TK2/PC26 D27/TD2/PC27 D28/RD2/PC28 D29/RK2/PC29 D30/RF2/PC30 D31/PCK1/PC31
U2 P6 T4 U3 R6 T6 U5 P7 R7 T7 T8 P8 R8 U8 R9 T9 P1 N2 M3 R1 T1 R2 P3 T2 P4 U1 T3 R4 P5 R5 P2 N3
D
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
G1 G2 H1 H2 J1 J2 K1 K4 K2 L1 K3 L2 L3 M1 N1 M2 D8 B8 A8 A7 B7 D7 A6 B6 C6 A5 D6 B5 A4 B4 A3 B3 A2 C4 B2 A1 B1 C2 C1 F2 J4 G3 E4 F1 H4 F4 D2 D1 G4 E3 E2 E1 F3 F15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22
RR1 100K
DDP DDM HDPA HDMA HDPB HDMB
J6
ICE INTERFACE
1 3 5 7 9 11 13 15 ICE_NRST 17 19 4 3 2 1
ICE_NTRST TDI TMS TCK ICE_RTCK TDO S4 S6 C12 4.7NF R11 C13 C14 4.7NF R12 C15 S2
AT91SAM9261
2 4 6 8 10 12 14 16 18 20
S3 NRST 3V3 S5
NBS0/A0 NWR2/NBS2/A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 BA0/A16 BA1/A17 A18 A19 A20 A21 A22 RAS CAS SDWE SDA10 SDCKE SDCK NCS0 SDCS/NCS1 NCS2 NANDCS/NCS3 CFOE/NRD CFWE/NWE/NWR0 CFIOR/NBS1/NWR1 CFIOW/NBS3/NWR3 NRST
G1 G2 G3 G4 G5
C
5 6 7 8
RAS CAS SDWE SDA10 SDCKE SDCK NCS0 SDCS_NCS1 NCS2 SMCS_NCS3 CFOE_NOE_NRD CFWE_NWE_NWR0 CFIOR_NBS1_NWR1 CFIOW_NBS3_NWR3 NRST 3V3 R13 1K
1,96K 1% 470pF 1,5K 1% 470pF S7 Y1 18.4320MHz
U9
U10 U12
PLLRCA XOUT
B
C16 10PF
B
1
DNP
2 4
J7
1 3 5
C17 10PF
2
S8 S9
U11
XIN
4
SMB MALE
C19 10PF C20 10PF
T10 VDDOSC C18 100NF T11 GNDOSC A10
32.768 kHz Y2
XOUT32
1
A11
XIN32
TST NC NC NC VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
C10 A9 C14 D10
R14 1K BP1
3V3 Z14
CR1225
J8
VDDCORE
VDDCORE
VDDCORE
+
3V
VDDCORE
VDDOSC + VDDPLL CURRENT MEASURE
GNDBU
VDDBU
R10 VDDPLL C21 100NF P9 GNDPLL WKUP SHDN
3
MN10 R1100D121C
1V2 R16 1,50M DNP R17 100K
RESET
3V3 C43 10F 10V
A
B11
K14
P12
A16 C7 C11 D3 H8 H9 H10 J3 J8 J9 J10 K8 K9 K10 R3 R16 U4 U7
P11
C15
D11
P15
D9
B9
C9
D5
C3
C5
C8
D4
H3
N4
J14
M4
GND
A
J10
J9
3 2 1
OUT
VDD
U6
L4
T5
2
R15
1K WAKE UP C126 100NF C22 100NF VDDBU SHDN WKUP C24 C26 100NF 100NF C23 C25 C27 J12 10F 100NF 100NF 1V2 10V VDDCORE CURRENT MEASURE
5
1
Wednesday, September 14, 2005
C28 10F 10V C29 C31 C33 C35 100NF 100NF 100NF 100NF C30 C32 C34 100NF 100NF 100NF C36 C38 C40 C42 100NF 100NF 100NF 100NF C37 C39 C41 100NF 100NF 100NF
C B A INIT EDIT
REV MODIF.
JPG JPG JPG
DES.
14/09/05 04/20/05 02/23/05
DATE
XXX
VER. REV.
XX/XX/05
DATE SHEET
BP2
AT91SAM9261-EK
AT91SAM9261
SCALE
1/1
1
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2 6
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
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EBI SDRAM INTERFACE
A[0..22] D[0..31] RAS CAS
D
SDWE SDA10 SDCKE SDCK CFIOR_NBS1_NWR1 CFIOW_NBS3_NWR3 SDCS_NCS1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 SDA10 A13 A16 A17 A14 SDCKE SDCK BA0 BA1 23 24 25 26 29 30 31 32 33 34 22 35 20 21 36 40 37 38
D
MN4 A0 MT48LC16M16A2 DQ0 A1 DQ1 A2 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 DQ8 A9 DQ9 A10 DQ10 A11 DQ11 DQ12 BA0 DQ13 BA1 DQ14 DQ15 A12 N.C VDD VDD CKE VDD VDDQ CLK VDDQ VDDQ DQML VDDQ DQMH VSS CAS VSS RAS VSS VSSQ VSSQ WE VSSQ CS VSSQ 2 4 5 7 8 10 11 13 42 44 45 47 48 50 51 53 1 14 27 3 9 43 49 28 41 54 6 12 46 52 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 3V3 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 SDA10 A13 A16 A17 A14 SDCKE SDCK BA0 BA1 23 24 25 26 29 30 31 32 33 34 22 35 20 21 36 40 37 38
MN5 A0 MT48LC16M16A2 DQ0 A1 DQ1 A2 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 DQ8 A9 DQ9 A10 DQ10 A11 DQ11 DQ12 BA0 DQ13 BA1 DQ14 DQ15 A12 N.C VDD VDD CKE VDD VDDQ CLK VDDQ VDDQ DQML VDDQ DQMH VSS CAS VSS RAS VSS VSSQ VSSQ WE VSSQ CS VSSQ 2 4 5 7 8 10 11 13 42 44 45 47 48 50 51 53 1 14 27 3 9 43 49 28 41 54 6 12 46 52 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 3V3
C
C
NBS0 A0 15 CFIOR_NBS1_NWR1 39 3V3 CAS RAS SDWE 17 18 16 19
NBS2 A1 15 CFIOW_NBS3_NWR3 39 CAS RAS C50 C51 C52 C53 100NF 100NF 100NF 100NF C44 C45 C46 100NF 100NF 100NF SDWE 17 18 16 19
R18 100K
C54 C55 C56 C57 100NF 100NF 100NF 100NF C47 C48 C49 100NF 100NF 100NF
S10
256 Mbits
256 Mbits
PA[0..31]
DUAL FOOTPRINT
D[0..31] PC[0..15] 3V3 A21 A22 PC0 PC1 PC14 PC15 WP 16 17 8 18 9 7 19 1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 34 35 MN6A CLE ALE RE WE CE R/B WP N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C MT29F2G16AABWP I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 N.C PRE N.C VCC VCC VSS VSS VSS 26 28 30 32 40 42 44 46 27 29 31 33 41 43 45 47 39 38 36 3V3 37 12 48 25 13 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A21 A22 PC0 PC1 PC14 PC15 WP 16 17 8 18 9 7 19 1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 25 26 MN6B CLE ALE RE WE CE R/B WP N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C VCC VCC VSS VSS K9F1208U0A-Y I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 29 30 31 32 41 42 43 44 48 47 46 45 40 39 38 35 34 33 28 27 37 12 36 13 3V3 D0 D1 D2 D3 D4 D5 D6 D7 PA0 PA1 PA2 SPI0_MISO SPI0_MOSI SPI0_SPCK SPI0_NPCS0 3V3 3 R20 100K RESET WP 5 S12 AT45DB321C-CNC WRITE PROTECT NORMALLY OPEN 3V3 J21 R72 10K 8 1 2 4 3V3 MN7 SO SI SCK CS VCC GND 6 7
B
C58 100NF
B
R19 100K
NRST PA3 1 2 3
S13
SD CARD / MMC CARD DATAFLASH CARD INTERFACE
J22 8 7 6 5 4 3 2 1 9 FPS009
PA4 PA0 PA2 PA1 PA6 PA5
MCDA1 SPI0_MISO MCDA0 SPI0_SPCK MCCK 3V3 SPI0_MOSI MCCDA SPI0_NPCS3 MCDA3 MCDA2 C115 100NF
C60 100NF C59 100NF
2 Gbits
A
512 Mbits
A
Wednesday, September 14, 2005
C B A INIT EDIT
REV MODIF.
JPG JPG JPG
DES.
14/09/05 04/20/05 02/23/05
DATE
XXX
VER. REV.
XX/XX/05
DATE SHEET
AT91SAM9261-EK
SDRAM & NANDFLASH
8 7 6 5 4 3 2
SCALE
1/1
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3 6
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
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3V3
D
DS2
GREEN
LINK&ACT
R21 R22 R24
1K 1K 1K
D
3V3 R23 4,7K
DS3 DS4
YELLOW FULL DUPLEX GREEN SPEED 100
Note1: 8/16 bit DataBus selection; Removed R27 when using 16-bit mode; otherwise is 8-bit mode.
3V3 MN8 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
3V3 VCCA
L1
742792093 C61 100NF
NC NC DVDD DVDD GPIO3 GPIO2 GPIO1 GPIO0 EECS/LED EECK EEDO EEDI DGND LINKACT# DUP# SPEED# CLK20MO DGND MDC MDIO DVDD TX_EN TXD3 TXD2 TXD1
DNP
D[0..15] A[0..22]
C
R27 4,7K
R25 49R9 1% TXD0 TX_CLK TEST5 RX_CLK RX_ER RX_DV COL CRS DGND RXD3 RXD2 RXD1 RXD0 LINK_I DVDD AVDD TXOTXO+ AGND AGND RXIRXI+ AVDD AVDD BGRES 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
R26 49R9 1% 15 J13 1 TD+ C62 100NF 3 CT 2 TDTX2
C
NRST D15 D14 D13 D12 D11 D10 D9 D8 3V3 A2
PC[0..15]
R28 4,7K
PC11 FIQ
S14
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
DGND NC LINK_O WAKEUP PW_RST# DGND SD15 SD14 SD13 SD12 SD11 SD10 SD9 SD8 DVDD IO16 CMD SA4 SA5 SA6 SA7 SA8 SA9 DGND INT
16
J0026D21 TX+ 1
DM9000
7 RD+ 3V3 VCCA 6 CT 8 RDC63 100NF 75 R29 49R9 1% R30 49R9 1% 4 1nF 5 C64 100NF 75 75
RX+
3
RX-
6
4 5
75
7 8
IOR# IOW# AEN IOWAIT DVDD SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 RST DGND TEST1 TEST2 TEST3 TEST4 DVDD X2_25M X1_25M DGND SD AGND
3V3
3V3
R31 6,80K 1%
B
R32 100K Y3 CFOE_NOE_NRD CFWE_NWE_NWR0 NCS2 1 S15 C66 22PF 2 25MHz C67 22PF 3V3 L2 4.7H C77 100NF VCCA 3V3 3V3 C68 100NF 3V3 C69 100NF 3V3 C70 100NF 3V3 C71 100NF 3V3 C72 100NF C73 100NF VCCA VCCA C75 100NF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
B
D0 D1 D2 D3 D4 D5 D6 D7 PC10 RST
C76 10F 10V 3V3 R70 0R R34 4,7K
C78 10F 10V
C79 100NF
C74 100NF
R71 0R
PC2
NWAIT NOT USED
S16
A
A
Wednesday, September 14, 2005
C B A INIT EDIT
REV MODIF.
JPG JPG JPG
DES.
14/09/05 04/20/05 02/23/05
DATE
XXX
VER. REV.
XX/XX/05
DATE SHEET
AT91SAM9261-EK
ETHERNET
8 7 6 5 4 3 2
SCALE
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This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
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3V3 PA[0..31] PA12 PA2 PA1 PA0 PA28 PA11 PC2 SPI0_SPCK SPI0_MOSI SPI0_MISO SPI0_NPCS2 BUSY IRQ0 3V3 L5 C120 10F 10V C122 100NF C121 C123 100NF 100NF 4.7H PC[0..15]
3V3 54132-4097 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 J23 C124 100NF C125 10V 10F X_RIGHT Y_LOW X_LEFT Y_UP VCTRL Vctrl PCI PB23 B0 LCDD18 PB24 B1 LCDD19 PB25 B2 LCDD20 B3 B4 B5 G0 G1 G2 G3 G4 G5 R0 R1 R2 R3 R4 R5 LCDD21 LCDD22 LCDD23 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14 LCDD15 LCDD2 LCDD3 LCDD4 LCDD5 LCDD6 LCDD7 PB26 PB27 PB28 PB15 PB16 PB17 PB18 PB19 PB20 PB7 PB8 PB9 PB10 PB11 PB12 PB4 LCDCC C84 100NF 3 X_LEFT Y_UP X_RIGHT Y_LOW R73 R76 R77 R78 0R 0R 0R 0R C116 10NF C119 10NF C117 C118 10NF 10NF R80 R81 1 2 Q6 IRLML2402 PA12 POWER CONTROL IN AGND TP65 TP66 ADS7843E 100K 100K TP63 7 8 TP64 GND 6 IN3 IN4
TOUCH SCREEN CONTROLLER
MN16 R75 10K MN11 1 2 3 4 RST IN N.C GND N.C N.C N.C N.C 8 7 6 5 2 3 4 5 XP YP XM YM DCLK DIN DOUT CS BUSY PENIRQ VREF VCC VCC 16 14 12 15 13 11 9 1 10
R84 100K R74 47R
D
M5V
S24 S25 S26
D
Z17 TX09D71VM1CCA
C87 4.7NF
R79 0R
MC34064D
DNP
R82 0R
TWO USER'S ANALOG INPUTS Full-Scale Input Span 0 to VREF R83 10K VCTRL
C
DTMG LCDDEN HSYNCLCDHSYNC
PB3 PB1
C
DCLK LCDDDOTCK PB2
3V3
PB[0..31]
PA[0..31]
B B
PA27
BP3
3V3
GREEN
R50
220R
S19 PA14 PA26 BP4
DS7
GREEN
R51
220R
S20 PA13 PA25 BP5
DS8
A
PA24
BP6 Wednesday, September 14, 2005
A
USER INTERFACE
C B A INIT EDIT
REV MODIF.
JPG JPG JPG
DES.
14/09/05 04/20/05 02/23/05
DATE
XXX
VER. REV.
XX/XX/05
DATE SHEET
AT91SAM9261-EK
LCD & USER'S INTERFACE
8 7 6 5 4 3 2
SCALE
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This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
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C91 100NF
MN13 1 C1+
3V3 VCC
16 15 2
C92 100NF C93 100NF C95 100NF MALE RIGHT ANGLED J15
C94 100NF R52 0R
D
3 C14 C2+
GND V+
5 C211
T
V-
6 14
SERIAL DEBUG PORT
RXD TXD
EXPANSION CONNECTORS
PA10 PA[0..31] PB[0..31] PC[0..15] J16 J17 S21 PA9
DBGU_TXD 10 DBGU_RXD 12
T R
7 13
1 6 2 7 3 8 4 9 5
D
C
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 A[0..22]
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 D[0..31]
PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15
PB0 PB2 PB4 PB6 PB8 PB10 PB12 PB14 PB16 PB18 PB20 PB22 PB24 PB26 PB28 PB30 PA0 PA2 PA4 PA6 PA8 PA10 PA12 PA14 PA16 PA18 PA20 PA22 PA24 PA26 PA28 PA30 PC0 PC2 PC4 PC6 PC8 PC10 PC12 PC14 D16 D18 D20 D22 D24 D26 D28 D30
B
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31
NRST VDDBU 3V3 5V
1.27 PITCH
PB30 NRST
USB_DP_PUP
1 4 2 3 GND
SN74LVC1G00DBV C102 100NF
1
3V3
5V R64 1,5K 2.54 PITCH
3
2
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120
PB1 PB3 PB5 PB7 PB9 PB11 PB13 PB15 PB17 PB19 PB21 PB23 PB25 PB27 PB29 PB31 PA1 PA3 PA5 PA7 PA9 PA11 PA13 PA15 PA17 PA19 PA21 PA23 PA25 PA27 PA29 PA31 PC1 PC3 PC5 PC7 PC9 PC11 PC13 PC15 D17 D19 D21 D23 D25 D27 D29 D31
A1 A4 A7 A11 A13 A15 A18 A0 A10 A17 A21 A22 SDCS_NCS1 CFIOR_NBS1_NWR1 CFOE_NOE_NRD CFIOW_NBS3_NWR3 RAS SDWE CAS D2 D3 D10 D8 D12 D11 D6 D9
3V3 3V3 5V
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80
10
5V F1 500 mA
A2 A3 A6 A9 A12 A14 A16 A19 A5 A8 A20
9
R ADM3202ARN
8
SDCKE NCS2 CFWE_NWE_NWR0 SDA10 NCS0 SDCK D1 D0 D5 D7 D4 D15 D13 D14 SMCS_NCS3 HDMA HDPA
11
F2 500 mA
C
R53 0R
J18
CCUSBA-32002-30X
USB HOST INTERFACE
R54 R55 39R 39R R56 15K R57 15K C96 47pF C97 47pF C98 100NF
A1 A2 A3 A4
A B
B1 B2 B3 B4 34
C99 100NF
12
3V3 3V3 5V HDMB HDPB
R58 R59
39R 39R R60 15K R61 15K C100 47pF C101 47pF
S22 PB29 USB_CNX
R62 15K
B
USER'S GRID AERA
WKUP SHDN 3V3 5V 3V3 5V R63 22K 3V3 MN14 VCC NOT POPULATED Q5 IRLML6302
5
USB DEVICE INTERFACE
DDM DDP C105 15PF R65 R66 C106 15PF 39R 39R
J19 C103 33PF
2 3 5 6
1 4
C104 100NF
A
A
Wednesday, September 14, 2005
C B A INIT EDIT
REV MODIF.
JPG JPG JPG
DES.
14/09/05 04/20/05 02/23/05
DATE
XXX
VER. REV.
XX/XX/05
DATE SHEET
AT91SAM9261-EK
SERIAL & I/O EXPANSION
SCALE
1/1
1
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6 6
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
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2
Atmel Corporation
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
Atmel Operations
Memory
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314
RF/Automotive
Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759
Regional Headquarters
Europe
Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500
Microcontrollers
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60
Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom
Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80
Asia
Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369
ASIC/ASSP/Smart Cards
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